EDN

SystemVerilog reference verification methodology: Introduction

Verification is the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. Traditional verification methods struggle to keep pace with the ever-increasing size ...
Semiconductor Engineering

Adding Value To Open-Source RISC-V Cores With Verification

Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the ...
Semiconductor Engineering

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious.
EDN

SystemVerilog reference verification methodology: RTL

SystemVerilog enables such a unified approach, since code coverage, functional coverage points, and assertions are all defined by the same language. Using formal analysis The VMM for SystemVerilog ...