Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
EDN

Simplify FPGA Design and Test Projects

During the 2012 Design West conference and exhibition I talked with Frederic Leens, founder of Byte Paradigm, about a new approach to “instrument” and test designs within an FPGA. Byte Paradigm ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
Design-Reuse

Transitioning to Advanced Verification Techniques for FPGAs - Catch-22?

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques ...
New Electronics

First integrated FPGA-in-the-loop workflow for PolarFire and SmartFusion2 FPGA development boards

Microsemi has announced a collaboration with MathWorks to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi FPGA development ...
EDN

Create your perfect electronics test bench: mid-range to high-end

As we discussed in the earlier article on entry-level test benches, there are key pieces of equipment that every test bench should have regardless of level. What’s different about mid-level and ...
Semiconductor Engineering

Using FPGAs For Emulation

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big ...