Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
New Electronics

Faster FPGA verification

Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry. Today, design verification accounts for more than ...
New Electronics

Aldec adds UVM Generator to Riviera-PRO

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO. The addition is ...
Business Wire

Agnisys Offers Free Register Generator for UVM

SAN JOSE, Calif.--(BUSINESS WIRE)--Agnisys today announced a free version of its Hardware Specification tool – IDesignSpec™. It enables users to capture hardware specification that is automatically ...
Design-Reuse

Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...
Design-Reuse

Mentor Graphics Adds Memory Models to Create Industry's First Complete UVM SystemVerilog Verification IP Library

WILSONVILLE, Ore., Feb. 29, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of the first entirely native UVM SystemVerilog memory verification IP library for all ...
Electronics Weekly

FPGA functional verification: why bother?

FPGA engineers are all doing functional verification using manual processes but growing system comlexity is the issue. Changing tools and methodologies may seem daunting, but there is a way to break ...
Semiconductor Engineering

Experts At The Table: Verification Strategies

System-Level Design sat down to discuss verification strategies and changes with Harry Foster, chief verification scientist at Mentor Graphics: Janick Bergeron, verification fellow at Synopsys; Pranav ...
Design-Reuse

Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
elEconomista

DVCon Europe "Must See": Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

Aldec verification expert Alex Grove will give a real-world example of the use of Easier UVM, following on from an introduction by Doulos earlier in the DVCon conference. “ Many verification teams may ...